Semiconductor dice are becoming ever-smaller in dimension, both from advances in fabrication technology and as so-called “shrinks” of initial semiconductor die designs are developed to increase the number of dice which may be fabricated on a wafer or other bulk semiconductor substrate. As a consequence, it becomes more difficult to employ lead frame-based packaging techniques using, for example, wire bonds to directly connect bond pads of a die to lead fingers of a lead frame due to diminishing size of bond pads as well as decreasing pitch (spacing) between adjacent bond pads, rendering it difficult, if not impossible in some circumstances, to place inner ends of lead fingers of a lead frame in close proximity to bond pads to which they are to be wire bonded. In addition, below a certain minimum bond pad size and pitch, it becomes impossible to position a wire bonding capillary head accurately enough to avoid contact with, and possible damage to, adjacent bond pads.
Further, when bond pads are arranged along a central axis of a semiconductor die, such as is conventional in so-called “leads over chip,” or “LOC” packages, one may be faced with a choice between elongating and overcrowding lead fingers to place them in close proximity to the bond pads, or forming overly long wire bonds between the bond pads and remotely placed inner ends of lead fingers and risking potential breakage of the wire bonds or shorting between adjacent wire bonds when the package is being transfer-molded in an encapsulant by so-called “wire bond sweep” initiated by the flow front of the molten encapsulant moving over the active surface of the semiconductor die. The use of overly long wire bonds or extended lead fingers may also degrade signal integrity.
In addition, most conventional, lead frame-based packages do not facilitate high device density in conjunction with high multi-die device yields in terms of utilizing available “real estate” on a printed circuit board or other higher-level packaging.
Therefore, it would be desirable to provide a semiconductor device assembly packaging configuration which would accommodate ever-smaller semiconductor dice and their smaller, more closely pitched bond pads, and which would also facilitate the fabrication of highly reliable multi-die assemblies offering relatively high device densities.